Fundamentals of Logic Design, Enhanced Seventh Edition
By Charles H. Roth, Jr., Larry L. Kinney, and Eugene B. John
Contents:
Preface xiii
How to Use This Book for Self-Study xviii
Digital Resources xix
About the Authors xxiv
Unit 1 Introduction
Number Systems and Conversion 1
Objectives 1
Study Guide 2
1.1 Digital Systems and Switching Circuits 6
1.2 Number Systems and Conversion 8
1.3 Binary Arithmetic 12
1.4 Representation of Negative Numbers 16
Sign and Magnitude Numbers 16
2’s Complement Numbers 16
Addition of 2’s Complement Numbers 17
1’s Complement Numbers 19
Addition of 1’s Complement Numbers 19
1.5 Binary Codes 21
Problems 24
Unit 2 Boolean Algebra 29
Objectives 29
Study Guide 30
2.1 Introduction 36
2.2 Basic Operations 37
2.3 Boolean Expressions and Truth Tables 39
2.4 Basic Theorems 41
2.5 Commutative, Associative, Distributive, and
DeMorgan’s Laws 43
2.6 Simplification Theorems 46
2.7 Multiplying Out and Factoring 49
2.8 Complementing Boolean Expressions 52
Problems 53
Unit 3 Boolean Algebra (Continued) 60
Objectives 60
Study Guide 61
3.1 Multiplying Out and Factoring Expressions 66
3.2 Exclusive-OR and Equivalence Operations 68
3.3 The Consensus Theorem 70
3.4 Algebraic Simplification of Switching Expressions 72
3.5 Proving Validity of an Equation 74
Programmed Exercises 77
Problems 82
Unit 4 Applications of Boolean Algebra
Minterm and Maxterm Expansions 87
Objectives 87
Study Guide 88
4.1 Conversion of English Sentences to Boolean Equations 94
4.2 Combinational Logic Design Using a Truth Table 96
4.3 Minterm and Maxterm Expansions 97
4.4 General Minterm and Maxterm Expansions 100
4.5 Incompletely Specified Functions 103
4.6 Examples of Truth Table Construction 104
4.7 Design of Binary Adders and Subtracters 108
Problems 114
Unit 5 Karnaugh Maps 123
Objectives 123
Study Guide 124
5.1 Minimum Forms of Switching Functions 134
5.2 Two- and Three-Variable Karnaugh Maps 136
5.3 Four-Variable Karnaugh Maps 141
5.4 Determination of Minimum Expressions Using
Essential Prime Implicants 144
5.5 Five-Variable Karnaugh Maps 149
5.6 Other Uses of Karnaugh Maps 152
5.7 Other Forms of Karnaugh Maps 153
Programmed Exercises 154
Problems 159
Unit 6 Quine-McCluskey Method 167
Objectives 167
Study Guide 168
6.1 Determination of Prime Implicants 173
6.2 The Prime Implicant Chart 176
6.3 Petrick’s Method 179
6.4 Simplification of Incompletely Specified Functions 181
6.5 Simplification Using Map-Entered Variables 182
6.6 Conclusion 184
Programmed Exercise 185
Problems 189
Unit 7 Multi-Level Gate Circuits
NAND and NOR Gates 193
Objectives 193
Study Guide 194
7.1 Multi-Level Gate Circuits 199
7.2 NAND and NOR Gates 204
7.3 Design of Two-Level NAND- and NOR-Gate Circuits 206
7.4 Design of Multi-Level NAND- and NOR-Gate Circuits 209
7.5 Circuit Conversion Using Alternative Gate Symbols 210
7.6 Design of Two-Level, Multiple-Output Circuits 214
Determination of Essential Prime Implicants for
Multiple-Output Realization 216
7.7 Multiple-Output NAND- and NOR-Gate Circuits 217
Problems 218
Unit 8 Combinational Circuit Design
and Simulation Using Gates 225
Objectives 225
Study Guide 226
8.1 Review of Combinational Circuit Design 229
8.2 Design of Circuits with Limited Gate Fan-In 230
8.3 Gate Delays and Timing Diagrams 232
8.4 Hazards in Combinational Logic 234
8.5 Simulation and Testing of Logic Circuits 240
Problems 243
Design Problems 246
Seven-Segment Indicator 246
Unit 9 Multiplexers, Decoders, and Programmable
Logic Devices 252
Objectives 252
Study Guide 253
9.1 Introduction 260
9.2 Multiplexers 261
9.3 Three-State Buffers 265
9.4 Decoders and Encoders 268
9.5 Read-Only Memories 271
9.6 Programmable Logic Devices 275
Programmable Logic Arrays 275
Programmable Array Logic 278
9.7 Complex Programmable Logic Devices 280
9.8 Field-Programmable Gate Arrays 282
Decomposition of Switching Functions 283
Problems 286
Unit 10 Introduction to VHDL 294
Objectives 294
Study Guide 295
10.1 VHDL Description of Combinational Circuits 299
10.2 VHDL Models for Multiplexers 304
10.3 VHDL Modules 306
Four-Bit Full Adder 308
10.4 Signals and Constants 311
10.5 Arrays 312
10.6 VHDL Operators 315
10.7 Packages and Libraries 316
10.8 IEEE Standard Logic 318
10.9 Compilation and Simulation of VHDL Code 321
Problems 322
Design Problems 327
Unit 11 Latches and Flip-Flops 331
Objectives 331
Study Guide 332
11.1 Introduction 336
11.2 Set-Reset Latch 338
11.3 Gated Latches 342
11.4 Edge-Triggered D Flip-Flop 346
11.5 S-R Flip-Flop 349
11.6 J-K Flip-Flop 350
11.7 T Flip-Flop 351
11.8 Flip-Flops with Additional Inputs 352
11.9 Asynchronous Sequential Circuits 354
11.10 Summary 357
Problems 358
Programmed Exercise 367
Unit 12 Registers and Counters 370
Objectives 370
Study Guide 371
12.1 Registers and Register Transfers 376
Parallel Adder with Accumulator 378
12.2 Shift Registers 380
12.3 Design of Binary Counters 384
12.4 Counters for Other Sequences 389
Counter Design Using D Flip-Flops 393
12.5 Counter Design Using S-R and J-K Flip-Flops 395
12.6 Derivation of Flip-Flop Input Equations—Summary 398
Problems 402
Unit 13 Analysis of Clocked Sequential Circuits 412
Objectives 412
Study Guide 413
13.1 A Sequential Parity Checker 419
13.2 Analysis by Signal Tracing and Timing Charts 421
13.3 State Tables and Graphs 425
Construction and Interpretation of Timing Charts 430
13.4 General Models for Sequential Circuits 432
Programmed Exercise 436
Problems 441
Unit 14 Derivation of State Graphs and Tables 453
Objectives 453
Study Guide 454
14.1 Design of a Sequence Detector 457
14.2 More Complex Design Problems 463
14.3 Guidelines for Construction of State Graphs 467
14.4 Serial Data Code Conversion 473
14.5 Alphanumeric State Graph Notation 476
14.6 Incompletely Specified State Tables 478
Programmed Exercises 480
Problems 486
Unit 15 Reduction of State Tables
State Assignment 497
Objectives 497
Study Guide 498
15.1 Elimination of Redundant States 505
15.2 Equivalent States 507
15.3 Determination of State Equivalence Using an
Implication Table 509
15.4 Equivalent Sequential Circuits 512
15.5 Reducing Incompletely Specified State Tables 514
15.6 Derivation of Flip-Flop Input Equations 517
15.7 Equivalent State Assignments 519
15.8 Guidelines for State Assignment 523
15.9 Using a One-Hot State Assignment 528
Problems 531
Unit 16 Sequential Circuit Design 545
Objectives 545
Study Guide 546
16.1 Summary of Design Procedure for Sequential Circuits 548
16.2 Design Example—Code Converter 549
16.3 Design of Iterative Circuits 553
Design of a Comparator 553
16.4 Design of Sequential Circuits Using ROMs and PLAs 556
16.5 Sequential Circuit Design Using CPLDs 559
16.6 Sequential Circuit Design Using FPGAs 563
16.7 Simulation and Testing of Sequential Circuits 565
16.8 Overview of Computer-Aided Design 570
Design Problems 572
Additional Problems 578
Unit 17 VHDL for Sequential Logic 585
Objectives 585
Study Guide 586
17.1 Modeling Flip-Flops Using VHDL Processes 590
17.2 Modeling Registers and Counters
Using VHDL Processes 594
17.3 Modeling Combinational Logic Using VHDL Processes 599
17.4 Modeling a Sequential Machine 601
17.5 Synthesis of VHDL Code 608
17.6 More About Processes and Sequential Statements 611
Problems 613
Simulation Problems 624
Unit 18 Circuits for Arithmetic Operations 626
Objectives 626
Study Guide 627
18.1 Serial Adder with Accumulator 629
18.2 Design of a Binary Multiplier 633
18.3 Design of a Binary Divider 637
Programmed Exercises 644
Problems 648
Unit 19 State Machine Design with SM Charts 660
Objectives 660
Study Guide 661
19.1 State Machine Charts 662
19.2 Derivation of SM Charts 667
19.3 Realization of SM Charts 672
Problems 677
Unit 20 VHDL for Digital System Design 684
Objectives 684
Study Guide 685
20.1 VHDL Code for a Serial Adder 688
20.2 VHDL Code for a Binary Multiplier 690
20.3 VHDL Code for a Binary Divider 700
20.4 VHDL Code for a Dice Game Simulator 702
20.5 Concluding Remarks 705
Problems 706
Lab Design Problems 709
A Appendices 713
A MOS and CMOS Logic 713
B VHDL Language Summary 719
C Tips for Writing Synthesizable VHDL Code 724
D Proofs of Theorems 727
E Answers to Selected Study Guide Questions and Problems 729
References 785
Index 786
Description of the CD 792